The present invention relates to a graphics display controller and, more particularly, to a timing circuit in a display controller for generating a timing signal that is used for accessing a display memory to read display data therefrom.
A graphics display controller controls a display memory and a display device such as a raster-scan type cathode ray tube (called hereinafter "CRT") to display characters and figures on the screen of the CRT in accordance with data stored in the display memory.
The control of the display memory by the display controller may be divided into two major operations, one of which is a display operation wherein the display controller supplies a display address to the display memory to read data to be displayed, therefrom. That data being in turn supplied to the CRT, and the other of which is a drawing operation wherein the display controller supplies a memory address to the display memory to write or read display data therein or therefrom. The display data written in the display memory may be read out of the memory and then supplied to the CRT for being displayed. Since the controller is connected to the memory through a common address/data bus, it performs alternatively the display operation or the drawing operation in a time sharing manner. The display operation has of course priority over the drawing operation, because the data to be displayed must be read out of the display memory and supplied to the CRT in synchronism with the scanning speed thereof. Therefore, if a memory, which reads out data therefrom only a few bits per access, is employed as the display memory, the display controller is required to perform the display operation many times. Thus, a time allocated to perform the drawing operation is reduced, resulting in a lower speed for writing display data into the display memory.
In order to improve the drawing speed, there has been proposed a graphics display system that employs as a display memory a dynamic random access memory equipped internally with a serial data-read port including a line buffer. In such a memory, a great number of memory cells can be accessed simultaneously by one address and data read therefrom can be transferred to the line buffer in response to a timing signal externally supplied. The data stored in the line buffer is then read out in series one bit by one bit in synchronism with a serial clock also externally, supplied. In the graphics display system employing such a memory as a display memory, the display controller supplies a display address to the display memory together with a timing signal that is used for transferring the data read out of the accessed memory cells to the line buffer. Thus, by one access to the display memory, data stored in a great number of bits can be outputted therefrom. One bit of the display memory corresponds to one picture element in the screen of the CRT. Accordingly, a time required to perform the display operation is reduced. A time allocated to perform a drawing operation is in turn increased. The data drawing is thus carried out at a high speed.
Since each picture element of the CRT display screen corresponds to each bit of the display memory, the position of each picture element can be defined by the address of the corresponding bit. With respect to an address mapping of the display memory, there are two types, the first type being a memory in which the address space is larger than an addressable area in the CRT screen in both horizontal and vertical directions, and the second type being a memory in which the address space is the same as the addressable area in the CRT screen at least in the horizontal direction. In the first address mapping type, a so-called scrolling function can be performed in both horizontal and vertical directions only by changing a starting display address. However, the end display address of some horizontal scan line on the CRT screen is not successive to the start display address of the next horizontal scan line. For this reason, the controller is required to perform the display operation, i.e. access for display to the memory, each time the horizontal scan line to be displayed is changed. In the second address mapping type, on the other hand, the end display address of some horizontal scan line continues to the start display address of the next horizontal scan line. Accordingly, the access to the memory for displaying one picture plane on the screen can be achieved by designating a start address for the first horizontal scan line without needing the designation of the start address for the remaining horizontal scan lines. A time allocated to perform the drawing operation, i.e. access to the memory for drawing, can thereby be further increased. Needless to say, the access to the memory for display is required in both the first and second address mapping types when all the data stored in the line buffer has been outputted, i.e. when the line buffer becomes vacant.